1. Field of the Invention
The invention relates to a mobile communication transmitter/receiver and a method of transmitting/receiving digital signals, and more particularly to an analog baseband processor and a method of processing an analog baseband in a multimode communication system.
2. Description of the Related Art
Multiple modes of wireless communications (i.e. mobile communication standards/protocols) are available to allow mobile terminals (e.g., cell phones, PDAs, laptop computers) communicate in a mobile communication network. These modes are implemented over communication protocols including global system for mobile communications (GSM), general packet radio service (GPRS), wideband code division multiple access (WCDMA), CDMA2000, and time division-synchronous code division multiple access (TD-SCDMA).
In general, in a digital communication system, an analog signal is converted to a digital signal or a digital signal to an analog signal.
In a digital communication system, an analog-to-digital conversion or digital-to-analog conversion is typically required (e.g., to reduce noise on a transmission path and to improve transmission performance).
FIG. 1 is a block diagram illustrating a conventional digital communication transmitter/receiver.
Referring to FIG. 1, the conventional digital communication transmitter/receiver includes an RF processor 102, an IF processor 104, an analog baseband (ABB) processor 106 and a digital baseband (DBB) processor 108.
The receiving/transmitting schemes of the related art are largely classified between a homodyne scheme and a heterodyne scheme. The heterodyne scheme uses an intermediate frequency (IF) signal having a lower frequency than a RF signal in the reception/transmission, so that, in the transmitting and receiving system, amplification may be easily performed and selectivity and fidelity may be high.
When the digital communication transmitter/receiver receives a radio frequency (RF) signal (reception mode), the RF processor 102 converts the radio frequency (RF) signal received from an antenna to an intermediate frequency (IF) (by heterodyne techniques), or alternatively converts the RF signal directly to a baseband frequency (Direct Conversion, using zero-intermediate-frequency; homodyne). When the digital communication transmitter/receiver transmits the radio frequency (RF) signal (transmission mode), the RF processor 102 modulates an IF signal or a baseband signal to the RF signal to transmit the RF signal through the antenna.
The IF processor 104 is employed in a heterodyne transmitter/receiver (using the intermediate frequency (IF) signal). During reception mode, the IF processor 104 converts the IF signal into the baseband frequency, and during transmission mode, the IF processor 104 converts the baseband signal into the IF signal.
During reception mode, the analog baseband (ABB) processor 106 performs analog-to-digital conversion of an analog baseband signal and converts the analog baseband signal into a digital baseband signal (at an appropriate sampling rate or sampling frequency). The converted baseband signal is transmitted to the digital baseband (DBB) processor 108. During transmission mode, the analog baseband (ABB) processor converts a digital signal into an analog baseband signal (by performing a digital-to-analog conversion ADC of the received digital signal) to output an analog baseband signal to the IF processor 104.
The digital baseband (DBB) processor 108 performs signal demodulation and channel decoding in the reception mode, and performs signal modulation and channel coding in the transmission mode.
FIG. 2 is a block diagram illustrating a conventional analog baseband processor.
Referring to FIG. 2, the conventional analog baseband processor 200 includes an analog baseband receiver section 210 and an analog baseband transmitter section 230.
The analog baseband receiver section 210 includes an analog-to-digital converter (ADC) 212 and a first digital front end 213. The first digital front end 213 includes a decimator 214 and a first sample rate converter 216.
The analog-to-digital converter (ADC) 212 converts an analog baseband signal to a digital baseband signal (using a first predetermined sampling rate to generate a discrete time signal). The first digital front end 213 filters the digital (discrete time) baseband signal (using a second predetermined sampling rate) to supply the filtered digital baseband signal to a digital baseband processor 240.
The decimator 214 includes a first low pass filter (LPF1) 2141 and a first down-sampler 2143. The decimator 214 reduces the sampling rate (frequency) of the converted digital baseband signal (discrete time signal). The decimator 241 resamples the discrete time signal (digital baseband signal). The decimation is performed using a first down-sampler 2143 having a down sampling factor R1 (R1 is an integer). Therefore, where the digital (discrete time) signal inputted to the decimator 214 has a sampling rate of f1, an (resampled) output signal of the decimator 214 has the sampling rate of f1/R1. Aliasing in the resampled discrete time signal is avoided by using the first low pass filter 2141 to filtering the discrete time signal.
The first sample rate converter 216 includes a first up-sampler 2161, a second low pass filter 2163 and a second down-sampler 2165 to perform a (second) sampling rate conversion (with a fractional factor). The first up-sampler 2161 has an up-sampling factor M1 so that an output signal of the decimator 214 is up-sampled with the factor M1 (M1 is an integer). The second low pass filter 2163 prevents aliasing due to the up sampling conversion. The second down-sampler 2165 has a down-sampling factor L1 so that an output signal of the second low pass filter 2163 is down-sampled by the factor L1 (L1 is an integer). Thus, the first sample rate converter 216 converts the sampling rate of the output signal of the decimator 214 with a sampling rate conversion factor M1/L1. Therefore, a signal outputted from the first sample rate converter 216 has a (converted) sampling rate of f1c equal to f1/R1×M1/L1. Thus, f1c=f1×M1/(R1×L1).
The analog baseband transmitter unit 230 includes a digital-to-analog converter 236 and a second digital front end 231 for transmission. The second digital front end 231 includes a second sample rate converter 232 and an interpolator 234. The second sample rate converter 232 converts the sampling rate of an output signal of the digital baseband processor 240 with a fractional factor (M2/L2). For example, when the output signal of the digital baseband processor 240 has a sampling rate of f2/P2×L2/M2 (i.e., f2×L2/(P2×M2)), the second sample rate converter 232 includes a second up-sampler 2321 having an up-sampling factor M2 (M2 is an integer), a third low pass filter 2323 (for preventing the aliasing due to the up conversion), and a third down-sampler 2325 having a down-sampling factor L2 (L2 is an integer) so that the output signal of the digital baseband processor 240 is up-sampled with the factor M2 and then down-sampled with the factor L2. Therefore, a signal outputted from the second sample rate converter 232 has a sampling rate of f2/P2.
The interpolator 234 includes a third up-sampler 2341 having an up-sampling factor P2 and a fourth low pass filter 2343. The output signal of the second sample rate converter 231, the output of the second down-sampler 2325, is up-sampled with the factor P2 by the third up-sampler 2341. The fourth low pass filter 2343 removes the aliasing due to the up conversion. Therefore, the sampling rate of an output signal of the interpolator 234 is f2.
The digital-to-analog converter 236 converts the digital signal (the output signal from the second sample rate converter 231) to an analog signal to transmit the converted analog signal to an RF signal processor or IF signal processor.
The sampling rate of a signal applied to the digital baseband processor 240 depends on the sampling rate f1 of the analog-to-digital converter 212, and upon the sampling factors R1, M1 and L1 of the first digital front end 213. In addition, the signal applied to the digital baseband processor 240 is also dependent on a communication protocol standard.
Similarly, the sampling rate of the output signal of the digital baseband processor 240 is also determined by the communication protocol standard.
For example, there are many different communication protocol standards, such as GSM communication standard of a time-division multiple access (TDMA) used in a digital communication system, and cdma2000 and W-CDMA communication standards of a code-division multiple access (CDMA) that are widely popular for 3rd generaton wireless and cellular standards.
In a multimode communication system where various communication systems conforming to different communication standards are employed, parallel digital front ends for processing signals complying with the different communication standards are included with the analog baseband processors.
FIG. 3 is a block diagram illustrating a conventional analog baseband processor in a dual (two) mode receiver.
Referring to FIG. 3, the conventional analog baseband processor for the dual mode receiver includes a first analog-to-digital converter (ADC) 300 employed in a GSM/EDGE mode system, a first digital front end 310, and a second analog-to-digital converter (ADC) 340 employed in a W-CDMA mode system and a second digital front end 350. The conventional analog baseband processor of FIG. 3 includes two analog-to-digital converters 300 and 340, for two communication standards. The first analog-to-digital converter (ADC) 300 samples at first predetermined sampling rate (frequency) f1. The second analog-to-digital converter (ADC) 340 samples at second predetermined sampling rate (frequency) f2. Ordinarily, sampling rates f1 and f2 are not equal to each other.
The analog baseband processor of FIG. 3 selectively processes a GSM/EDGE signal or W-CDMA signal. Each of the two digital front ends 310 and 350 have configurations and functions similar to the digital front end (213) described in FIG. 2. The first digital front end 310 includes a first decimator 320 and a first sample rate converter 330. The first decimator 320 has a first low pass filter (LPF1) 322 and a first down-sampler 324. The first sample rate converter 330 has a first up-sampler 332, a second low pass filter 334 and a second down-sampler 336).
Similarly, the second digital front end 350 includes a second decimator 360 and a second sample rate converter 370. The second decimator 360 includes a third low pass filter 362 and a third down-sampler 364. The second sample rate converter 370 includes a second up-sampler 372, a fourth low pass filter 374 and a second down-sampler 376.
To support multiple communication standards (such as 2nd generation GSM/EDGE (Enhanced Data rates for the GSM Evolution) and 3rd generation W-CDMA in an IMT-2000 communication system), a receiver needs multiple analog-to-digital converters and multiple digital front ends (e.g., one analog-to-digital converter (ADC) having a predetermined sampling rate for each of the different communication standards).
However, when two or more communication systems are incorporated into a dual mode or multimode transmitter/receiver, the chip size may be increased and design complexity may be also increased due to the increased number of analog-to-digital converters (ADCs) and digital front ends.